Electronics devices and capabilities have grown extremely common in daily life. Along with personal computers in the home, many individuals carry more than one productivity tool for various and sundry purposes. Most personal productivity electronic devices include some form of non-volatile memory. Cell phones utilize non-volatile memory in order to store and retain user programmed phone numbers and configurations when the power is turned off. PCMCIA cards utilize non-volatile memory to store and retain information even when the card is removed from its slot in the computer. Many other common electronic devices also benefit from the long-term storage capability of non-volatile memory in un-powered assemblies.
Non-volatile memory manufacturers that sell to the electronic equipment manufacturers require testers to exercise and verify the proper operation of the memories that they produce. Due to the volume of non-volatile memories that are manufactured and sold at consistently low prices, it is very important to minimize the time it takes to test a single part. Purchasers of non-volatile memories require memory manufacturers to provide high shipment yields because of the cost savings associated with the practice of incorporating the memory devices into more expensive assemblies with minimal or no testing. Accordingly, the memory testing process must be sufficiently efficient to identify a large percentage of non-conforming parts and preferably all non-conforming parts in a single test process.
As non-volatile memories become larger, denser and more complex, the testers must be able to handle the increased size and complexity without significantly increasing the time it takes to test them. Memory testers frequently run continuously, and test time is considered a major factor in the cost of the final part. As memories evolve and improve, the tester must be able to easily accommodate the changes made to the device. Another issue specific to testing non-volatile memories is that repeated writes to cells of the memories can degrade the overall lifetime performance of the part. Non-volatile memory manufacturers have responded to many of the testing issues by building special test modes into the memory devices. These test modes are not used at all by the purchaser of the memory, but may be accessed by the manufacturer to test all or significant portions of the memories in as little time as possible and as efficiently as possible. Some non-volatile memories are also capable of being repaired during the test process. The tester, therefore, should be able to identify: a need for repair; a location of the repair; the type of repair needed; and, must then be able to perform the appropriate repair. Such a repair process requires a tester that is able to detect and isolate a specific nonconforming portion of the memory. In order to take full advantage of the special test modes as well as the repair functions, it is beneficial for a tester to be able to execute a test program that supports conditional branching based upon an expected response from the device.
From a conceptual perspective, the process of testing memories is an algorithmic process. As an example, typical tests include sequentially incrementing or decrementing memory addresses while writing 0""s and 1""s into the memory cells. It is customary to refer to a collection of 1""s and 0""s being written or read during a memory cycle as a xe2x80x9cvectorxe2x80x9d, while the term xe2x80x9cpatternxe2x80x9d refers to a sequence of vectors. It is conventional for tests to include writing patterns into the memory space such as checkerboards, walking 1""s and butterfly patterns. A test developer can more easily and efficiently generate a program to create these patterns with the aid of algorithmic constructs. A test pattern that is algorithmically coherent is also easier to debug and use logical methods to isolate portions of the pattern that do not perform as expected. A test pattern that is generated algorithmically using instructions and commands that are repeated in programming loops consume less space in tester memory. Accordingly, it is desirable to have algorithmic test pattern generation capability in a memory tester.
Precise signal edge placement and detection is also a consideration in the effectiveness of a non-volatile memory tester. In order to identify parts that are generally conforming at a median while not conforming within the specified margins, a non-volatile memory tester must be able to precisely place each signal edge relative in time to another signal edge. It is also important to be able to precisely measure at which point in time a signal edge is received. Accordingly, a non-volatile memory tester should have sufficient flexibility and control of the timing and placement of stimuli and responses from the Device Under Test (memory).
Memory testers are said to generate transmit vectors that are applied (stimulus) to the DUT (Device Under Test), and receive vectors that are expected in return (response). The algorithmic logic that generates these vectors can generally do so without troubling itself about how a particular bit in a vector is to get to or from a particular signal pad in the DUT, as the memory tester contains mapping arrangements to route signals to and from the pins that contact the DUT. The collection of the algorithmic pattern generation, threshold setting, signal conditioning and comparison mechanisms, and the probes that connect that stuff to the DUT, is called a test site. In the simple case there is one DUT per test site.
Memory testers have interior test memory that is used to facilitate the test process. This interior test memory may be used for several purposes, among which are storing transmit vectors ahead of time, as opposed to generating them in real time, storing expected receive vectors, and storing a variety of error indications and other information concerning DUT behavior obtained during testing. (There are also housekeeping purposes internal to the operation of the memory tester that use RAM and that may appear to fall within the purview of the phrase xe2x80x9cinterior memory.xe2x80x9d These are private to the internal operation of the tester, tend to not be visible at the algorithmic level, and are comparable to executable instruction stores and to internal control registers. That memory is described as xe2x80x9cinterior control memory,xe2x80x9d and is excluded from what is meant herein by the term xe2x80x9cinterior test memory,xe2x80x9d which we use to describe memory used to store bit patterns directly related to the stimulus of, and response from, the DUT.) It is easy to appreciate that this interior test memory needs to operate at least as fast as the tests being performed; a very common paradigm is for the interior test memory (or some portion thereof) to be addressed by the same address (or some derivative thereof) as is applied to the DUT. What is then stored at that addressed location in interior test memory is something indicative of DUT behavior during a test operation performed on the DUT at that address. Algorithmic considerations within the test program may mean that the sequence of addresses associated with consecutive transmit vectors can be arbitrary. Thus, the interior memory needs to have the dual attributes of high speed and random addressability. SRAM comes to mind immediately as being fast, easy to control and tolerant of totally random addressing. Indeed, conventional memory testers have used SRAM as their interior test memory.
Unfortunately, SRAM is quite expensive, and this has limited the amount of interior test memory with which memory testers have had to work. The result is limits on memory tester functionality that are imposed by a shortage of memory. DRAM is significantly less expensive, but cannot tolerate random addressing and still perform at high speed.
DRAM can replace SRAM as the interior test memory in a memory tester. As briefly described below, the problem of increasing the speed of DRAM operation for use as interior test memory can be solved by increasing the amount of DRAM used, in place of increasing its speed. Numbers of identical Banks of DRAM are treated as Groups. A combination of interleaving signals for different Banks of memory in a Group thereof and multiplexing between those Groups of Banks slows the memory traffic for any one Bank down to a rate that can be handled by the Bank.
At the top level of interior test memory organization there are four Memory Sets, each having its own separate and independent address space and performing requested memory transactions. Two are of SDRAM as described above, and two are of SRAM. Each Memory Set has its own controller to which memory transactions are directed. As to externally visible operational capabilities as memories, all four Memory Sets are essentially identical. They differ only in their size of memory space and how they are internally implemented: The SRAM Memory Sets do not employ multiplexing and interleaving, since they are fast enough to begin with. Despite their independence, Memory Sets of the same type (of SRAM or of DRAM) may be xe2x80x9cstacked,xe2x80x9d which is to say treated a one larger address space.
Thus it is that the interior test memory of the tester is divided into four Memory Sets, two of which are xe2x80x9cinternalxe2x80x9d SRAM""s and two of which are xe2x80x9cexternalxe2x80x9d DRAM""s. To be sure, all this memory is physically inside the memory tester; the terms xe2x80x9cinternalxe2x80x9d and xe2x80x9cexternalxe2x80x9d have more to do with a level of integration. The SRAM""s are integral parts of a VLSI (Very Large Scale Integration) circuit associated with the tester""s central functional circuitry, while the DRAM""s are individual packaged parts mounted adjacent the VLSI stuff. The amount of SRAM is fairly small, (say, around a megabit per Memory Set) while the amount of DRAM is substantial and selectable (say, in the range of 128 to 1024 megabits per Memory Set). The SRAM Memory Sets are always present, and may be used for any suitable purpose, such as storing the expected content of a DUT that is a ROM (Read Only Memory). The DRAM Memory Sets, although actually optional, are typically used for creating a trace for subsequent analysis leading to repair, although there are also other uses. The tester need not, in principle, enforce distinctions between the SRAM and DRAM Memory Sets, as to different purposes for which they may be used. There are some practical distinctions that arise mostly as a matter of size; the SRAM Memory Sets are small, while the DRAM Memory Sets are potentially huge. The person or persons creating the test programming generally make the decisions concerning how the various Memory Sets are to be used. There are, however, a few distinctions where a particular operational feature of the memory tester requires the use of a specific Memory Set. These cases usually arise out of economic or performance considerations that require a dedicated hardware path to a Memory Set. While these mechanisms could be generalized, it is expedient to simply pick a likely one, and let it go at that.
The advent of substantial amounts of interior test memory (in the form of the DRAM Memory Sets) raises the issue of how this additional amount of memory can be used to facilitate the operation of desirable features within the memory tester. In the tester of interest the interior test memory subsystem is extremely flexible, in that despite having a native word width of thirty-two bits, the effective word width can be any power of two (up to 25=32), with a corresponding increase in address space for narrower words. There is an extensive address mapping capability, both for addressing DUT""s and for addressing interior test memory, substantial data classification and address classification mechanisms that facilitate multiple Tag RAM""s and other error analysis tools, all of which are made more practical by having lots of interior test memory. Moreover, these enhancements made possible by more memory do not exist in a vacuum; they are very valuable in the testing of certain types of memory parts.
It is conventional for a memory tester to have a capability called xe2x80x9cpost decode.xe2x80x9d The idea is that, after tests have been run on a DUT, the interior test memory, which may have been divided into several sections (variously organized as tables, lists, traces or xe2x80x9cimagesxe2x80x9d of events of interest), will contain data ready for inspection. For the most part, these inspections will be to discover indications of failure, and in the system of interest an indication of a failure is encoded by a zero. It is a bit of a simplification, but what is often needed, and what the Post Decode mechanism is frequently expected to do, is to tote up the number of 0""s in some structure in interior test memory. Prior art memory testers have heretofore required that the test data be stored in some memory structure in interior test memory, such as in an Error Catch RAM, before being applied to the Post Decode mechanism.
Prior art memory testers with a post decode capability have been limited in ways that are presently perceived as causing increased test time. Manufacturers of high volume memory parts believe that xe2x80x9ctime on the tester is moneyxe2x80x9d and are in favor of strategies that reduce test time. The advent of increased amounts of interior test memory, in conjunction with address and data classification techniques that allow the production of pluralities of xe2x80x9cTag RAM""sxe2x80x9d (tables whose entries have highly refined meanings, and are thus small in comparison with, say, a simple image of addresses versus error that is essentially equivalent in size to the DUT itself) have put conventional post decode techniques into the position of being a limiting factor for the task of reducing test time. This situation simply gets worse as memories (DUT""s) get larger and internally more complex. The increased complexity means there are more memory structures (Tag RAM""s, etc.) in interior test memory to apply to the post decode section, and the increased size of the DUT""s means those memory structures are also larger; all of which adds up to increases in test time.
What can be done to make the operation of post decode faster and more efficient? And, are there new types of measurements that an enhanced post decode can do that add to the utility of the memory tester?
A number of things can be done to enhance the operation of post decode. In the preferred embodiment described below, the data path into the post decode section is altered to allow post decode to process suitable data xe2x80x9con the fly,xe2x80x9d as it were, before or as that data is placed into a destination memory structure in interior test memory. Other data will continue to be first placed into a memory structure in interior test memory before being applied to the post decode mechanism. Extensive masking capability coupled with copies of error tables allow incremental post decode analysis for a new test, and avoids counting of errors in locations that are already known to have failed during a previous test(s). Errors can be accumulated with differing scopes, or resolution; both errors within words and bit errors can be accumulated. The internal architecture of an enhanced post decode mechanism is often capable of producing multiple types of results from a single pass through the data, whether applied on the fly or from a structure in interior test memory. The post decode mechanism has many counters therein, and they count down from pre-loaded values representing thresholds for deciding something about error activity. When a counter counts down to zero it produces a terminal count flag. The values of the various terminal count flags are available at any time as data to be stored (their values logged) in a structure in interior test memory. Finally, it is often the case that each counter is reloaded with its initial count at the conclusion of one test phase and in preparation for a subsequent phase. Some overhead may be saved and utility added by arranging for the counters to have respective initial value registers from which they may be reloaded upon receipt of a single command, as opposed to having to send those various initial values all over again via a bus. In addition, it is desirable to arrange that the presence of the terminal count flag for a counter can inhibit the reload of the counter from its initial value register.